In communication systems an oscillator is used as a fundamental building block. Oscillators are commonly used for up and down frequency conversion. They are also required for subsystems such as a direct modulator. The quality of a fixed frequency oscillator is measured by the frequency accuracy and the phase noise performance. In communication systems, the basic RF oscillator is used in conjunction with additional circuitry to stabilize the frequency of the oscillator as typical free running RF oscillators are not stable enough for most communication systems. It is well known that crystal oscillators provide a high degree of frequency accuracy and phase noise performance. Hence, it is common in prior art to lock the RF oscillator to a lower frequency crystal oscillator in order to achieve the desired frequency stability. Besides frequency stability, other qualities including the ability to tune a single oscillator over a wide frequency range, the ability of having a very fine frequency resolution control, and the ability to change the frequency very rapidly are quite imperative. Numerous prior art methods exist for the generation of an oscillator subsystem with varying degrees of compromises and limitations. Commonly used methods are discussed below and are described in more detail hereinafter in conjunction with the accompanying drawings.
The first method uses frequency multiplication wherein crystal oscillators that are commonly available at low frequencies are multiplied up using frequency multiplication. This method yields a high phase noise performance but suffers from very limited frequency agility.
The second method uses a phase locked loop (PLL). PLLs are available in a variety of forms such as fixed modulus, dual modulus, and fractional N. Many integrated circuit implementations are available. However a PLL with lower loop bandwidth thus has to be used which consequently degrades the phase noise.
The third method is a digital delay lock loop (DLL). This has the advantage that the oscillator is suitable for implementation in an ASIC. A variable delay control is used in conjunction with the phase detector to lock the oscillator frequency to a multiple of the input reference frequency. This method suffers from limitations to the PLL implementation. It also faces additional problems with frequency agility as well as the jitter introduced by the delay lock loop because of mismatched delays.
The fourth method is known as direct digital synthesis (DDS). This method results in very fine frequency resolution, but produces undesired spurious signals and the output signal frequency is limited by the speed of the DAC. The signal frequency for the DDS is limited to Nyquist frequency which is half of the clock frequency to the DAC. Output signal level drops as the Nyquist frequency is approached.
A fifth method is through phase interpolation as described in U.S. Pat. No. 6,114,914 (Mar) issued Sep. 5, 2000. This method is limited in its factional capability and still uses a VCO, phase detector, and loop filter. Normal conflict between better phase noise and higher frequency resolution still exists for this method.